Modern semiconductor based integrated circuits (ICs) are incredibly complex and contain millions of circuit devices, such as transistors, and millions of interconnections between the circuit devices. Designing such complex circuits cannot be accomplished manually, and circuit designers use computer based Electronic Design Automation (EDA) tools for schematics, layouts, simulation, and verification of the complex circuits. Furthermore, EDA tools allow circuit designers to optimize a complex electronic circuit, for example, by reducing the footprints of the various circuit devices. The current version of Moore's law states that the number of transistors per square inch in an IC doubles every eighteen months. Reducing the footprint of transistors and other circuit devices, for example, by keeping them closer together will keep the pace of the explosive and exponential growth of computing power, as foreseen by Moore's law.
EDA tools typically use instances of programmable cells or parameterized cells (a single instance generally shortened as a “pcell”) to form an electronic circuit design. The instances of pcells are connected through pins. For example, for a transistor pcell instance, the pins connecting the transistor pcell to other pcells in the design are a source pin, a drain pin, and a gate pin. A pin may include one or more connecting shapes, called pin figures. For the transistor pcell instance, a pin figure for the source pin may be rectangular. For optical fibers and transmission lines, a pin figure for the pins interconnecting the segments of the optical fibers and the transmission lines may be a circular.
An EDA tool may optimize an IC design by abutting pcell instances to reduce the device footprint of the pcell instances. In other words, the EDA tool may pack the pcell instances closer together or merge the pcells (by abutting) thereby saving valuable semiconductor space in the IC. For example, the EDA tool may detect that two pcell instances are sufficiently close to be abutted and may trigger an abutment process based on such detection. However, as described below, conventional EDA tools and pcell libraries are unnecessarily complex and computationally heavy and yet provide a restricted functionality.
FIG. 1A-1C show a conventional abutment process done by a conventional EDA tool. FIG. 1A shows two devices (transistors, as shown, each having a source pin S, drain pin D, and a gate pin) to be abutted together. Each of the devices has two rectilinear access directions, left and right. To abut these two devices, a conventional EDA tool first checks the access directions for the devices. The conventional EDA tool determines, based on these access directions, that the shown devices can be abutted such that the right edge of the device on the left can be aligned with the left edge of the device on the right. The conventional EDA tool then aligns the two devices as shown in FIG. 1B. More specifically, the drain pin D of the device on the left has been aligned with the source pin S on the device on the right. After the alignment, the conventional EDA tool calculates an offset for one or both of the aligned pins such that the aligned pins can be overlapped for further optimization. Based on the calculated offset, the conventional EDA tool overlaps the aligning pins as shown in FIG. 1C. The conventional EDA tool may then remove portions from one or more of the overlapped pins to generate the abutted optimized devices.
However, there are several technological problems with the conventional EDA tools employing the aforementioned steps. For instance, for every abutment, the conventional EDA tools have to undergo the edge alignment and make offset calculations to position pins for abutment, which makes the pcell library for the conventional EDA tools unnecessarily complex. Every pcell library must have an access direction for the edge alignment and have the code for calculating the offset for the overlapping. Using such a p-cell library is also computationally heavy because an EDA tool using that library has to align the devices and calculate the offset for every group of devices that are being abutted. In addition, the conventional approach is restrictive—it supports only rectilinear pin figure shapes because non-rectilinear shapes are not conducive to aligning by the steps discussed above. For example, two circular pin figure shapes will at best touch at a point and therefore will not align as the rectangular pin figures as described above. In addition, pin figure shapes having different sizes may not align with each other as the pin figure shapes described in FIGS. 1A-1C. Furthermore, the access directions in the conventional pcells are restricted to rectilinear x-y coordinates (right, left, top, and bottom), which is unable to provide an angular abutment. An angular abutment is crucial to ICs including photonics circuit devices such as fiber optic components and the conventional EDA therefore are unable to support abutting photonics circuit devices.
What is therefore required is a pcell library and EDA tools that solve the aforementioned problems of excess complexity and yet restricted functionality. What is therefore required is a simpler pcell library and EDA tools that use the pcell library for abutting any pin figure shape and size and at any angle.